Advances in electronic devices generally include reducing the size of the components that form integrated circuits. With smaller circuit components, the value of each unit area of a semiconductor wafer becomes higher. This is because the ability to use all of the wafer area for integrated circuit components improves. To properly form an integrated circuit that employs a much higher percentage of usable wafer area, it is critical that contaminant particle counts on the semiconductor wafer surface be reduced below levels which previously may have been acceptable. For example, minute particles of oxides and metals of less than 0.2 microns are unacceptable for many of the popular advanced circuit designs, because they can short out two or more conducting lines.
In order to planarize a semiconductor wafer and to remove unwanted particles, chemical mechanical polishing or chemical mechanical polish (hereinafter "CMP") process has become popular. CMP systems place a semiconductor wafer in contact with a polishing pad that rotates relative to the semiconductor wafer. The semiconductor wafer may be stationary, or it may also rotate on a carrier that holds the wafer. Problems of conventional methods of performing a chemical mechanical polish is that they produce nonuniform wafers and produce larger than desirable edge exclusion areas. Both of these problems impair operation of resulting electronic components formed from the semiconductor devices. Semiconductor wafer non-uniformity may cause undesirable layers not to be removed at some places and desirable layers to be removed at other places on the wafer surface. This causes various areas on the wafer surface to be unusable for forming semiconductor devices. Process uniformity from wafer to wafer is also important in CMP processing. Known CMP systems, however, suffer from significant wafer-to-wafer non-uniformities. This can also adversely affect the throughput and yield of the CMP process. Edge exclusion occurs when too much of the semiconductor wafer surface is polished at the edge of the wafer. This causes the outer edge of the wafer to be unusable for applications such as semiconductor device fabrication.
Another problem of known methods of and systems for chemical mechanical polishing a semiconductor device is that they have throughput limitations. Wafer polish throughput, like polish uniformity is an important process parameter because it directly affects the number of integrated circuits or other applications for which the fabrication facility may supply components for a given period of time.